In a radio frequency (RF) transceiver, a frequency synthesizer based on a phase-locked loop (also referred to as PLL) structure is widely used to generate a local oscillator (LO) signal in order to complete a frequency shift operation on an RF signal. Because of advantages in aspects such as locking time, integral phase noise, and design flexibility, a digital fractional frequency-division phase-locked loop that can implement both integer frequency division and fractional frequency division is more widely applied than an integer frequency-division phase-locked loop.
In the digital fractional frequency-division phase-locked loop, linear performance of a time-to-digital converter (TDC) that serves as an important analog component is a main factor that affects linear performance of the entire phase-locked loop system. Because greater approximation to linearity leads to less noise, improving the linear performance of the TDC is a key factor for ensuring that the digital fractional frequency-division phase-locked loop remains at a low noise level.
However, for a current common TDC structure, factors affecting linearity of the TDC mainly include component mismatch, layout design mismatch, and the like. Generally, improving the linearity of the TDC requires relatively great expense in aspects such as power consumption, area, and complexity, and therefore, it is difficult to improve the linearity of the TDC.